1. Field of the Invention
The embodiments of the invention generally relate to integrated circuits and, more specifically, to an integrated circuit and a method using integrated process steps to form bulk deep trench isolation structures and deep trench capacitor structures (e.g., incorporated into embedded dynamic random access memory (eDRAM) cells) for the integrated circuit.
2. Description of the Related Art
Bulk device isolation is becoming more difficult at advanced process nodes (e.g., (e.g., at 32 nm and beyond). However, due to the lack of voltage scaling, shallow trench isolation (STI)) depths alone are not sufficient. Thus, current solutions for bulk device isolation currently involve dual-depth trench isolation. Specifically, STI typically provides isolation between same type devices within a given well and deep trench isolation (DTI) provide isolation between NWELLS and PWELLS within which p-type field effect transistors (PFETs) and n-type field effect transistors (NFETs) are formed, respectively. Unfortunately, forming the deep trench component of dual-depth trench isolation can be very complex and expensive, making it difficult to meet required groundrules.